Applying genetic parallel programming to synthesize combinational logic circuits
Experimental results show that parallel programs can be evolved more easily than sequential programs in genetic parallel programming (GPP). GPP is a novel genetic programming paradigm which evolves parallel program solutions. With the rapid development of lookup-table-based (LUT-based) field programmable gate arrays (FPGAs), traditional circuit design and optimization techniques cannot fully exploit the LUTs in LUT-based FPGAs. Based on the GPP paradigm, we have developed a combinational logic circuit learning system, called GPP logic circuit synthesizer (GPPLCS), in which a multilogic-unit processor is used to evaluate LUT circuits. To show the effectiveness of the GPPLCS, we have performed a series of experiments to evolve combinational logic circuits with two- and four-input LUTs. In this paper, we present eleven multi-output Boolean problems and their evolved circuits. The results show that the GPPLCS can evolve more compact four-input LUT circuits than the well-known LUT-based FPGA synthesis algorithms.
IEEE Transactions on Evolutionary Computation
Cheang, S.,Lee, K.,& Leung, K. (2007). Applying genetic parallel programming to synthesize combinational logic circuits. IEEE Transactions on Evolutionary Computation, 11 (4), 503-520. http://dx.doi.org/10.1109/TEVC.2006.884044
This document is currently not available here.